Episode 38: The Future of Transistor Design and Advanced Packaging

The Circuit · 16 Oct 2023 · 33m · Episode 40

What this episode covers

Huiming Bu from IBM Research discusses the future of transistor design and advanced packaging with host Ben Bajarin. They explore the industry's transition from FinFET to nanosheet architectures and the emergence of 3D scaling via Vertical Transport FETs (VTFET) and Stacked FETs (SFET). Bu explains how chiplet technology and heterogeneous integration are accelerating compute density, allowing AMD's MI300X to reach 100 billion transistors seven years ahead of traditional scaling predictions. The conversation highlights the critical need for System Technology Co-optimization (STCO) and new EDA tools to manage the complexity of 2.5D and 3D IC designs.

Other shows on the same ground, closest first.

  • EE Times Current · 24m

    Transforming Compute Possibilities with Multi-Die Systems

    Shekhar Kapoor, Senior Director of Product Line Management at Synopsys, explains the industry's shift from monolithic SoCs to multi-die systems, driven by the limits of Moore's Law and the demand for high-performance computing. He details how technologies like 3D stacking, fan-out wafer scale, and the UCIE standard enable modular, heterogeneous integration for products like the Apple iPhone 15 camera and Tesla's Autopilot. Kapoor highlights Synopsys' role in providing the TDC compiler and comprehensive IP portfolios to facilitate this transition, noting over 100 active multi-die designs currently in development across AI, automotive, and data center markets.

  • EE Times Current · 33m

    Returning from Mars (Matt Damon Redux) | Apple & the Sun King | Chip Packaging

    Kevin Crewell of Curious Research details TSMC's advanced packaging innovations, including 2.5D, 3D stacking, and SOIC, explaining how chiplets and heterogeneous integration address diminishing returns from Moore's Law. Bellagio Ojo and Junko Yoshida analyze the impact of US-China trade wars on electronics forecasting, highlighting how political whims, such as Apple's tariff exemption, create unpredictable business environments. George Leopold discusses the engineering challenges of Mars missions, specifically focusing on Relativity Space's proposal to use 3D printing with in-situ resources to solve the return-from-Mars problem.

  • The Amp Hour · 1h 04m

    Leading Edge Analog with Joren Vaes

    Joren Vaes, a high-speed design engineer at SOFICS, explains the complexities of designing analog IP blocks for leading-edge semiconductor nodes like TSMC's 2 nm process. He details how designers navigate massive Process Design Kits (PDKs) with thousands of rules, utilizing advanced simulation tools from Cadence, Synopsys, and Siemens to manage parasitics across 18+ metal layers. The conversation covers the transition from FinFET to nanosheet architectures and the use of on-chip passive components, such as transformers, to achieve impedance matching at frequencies up to 50 GHz. Vaes also describes the rigorous verification workflow, including Design Rule Checks (DRC), Layout Versus Schematic (LVS), and parasitic extraction, which are critical before tape-out to millions of dollars in mask costs.

  • EE Times Current · 34m

    Whither Semiconductors? The Wheels on the Bus Go ‘Round and ‘Round

    Jim McGregor, co-founder of Tirias Research, discusses the evolving competitive landscape of the semiconductor industry, identifying Intel, AMD, and NVIDIA (following its potential acquisition of Arm) as the new dominant trio. He explains how the convergence of computing, connectivity, and intelligence is blurring traditional boundaries, with companies like Qualcomm, Samsung, and MediaTek competing across smartphones, servers, and automotive sectors. McGregor highlights the shift toward heterogeneous computing, specialized accelerators like DPUs, and the move away from monolithic dies toward multi-chip modules and advanced packaging to overcome Moore's Law limitations.

  • The Amp Hour · 1h 02m

    Discussing Chiplets with Ming Zhang

    Ming Zhang, co-founder and CEO of zGlue, explains how his company uses chiplet integration to create custom, highly miniaturized integrated circuits that combine off-the-shelf silicon components like Nordic microcontrollers and Bosch sensors. Zhang details the 'Omni chip' reference design, the 'smart fabric' substrate that enables programmable interconnects, and the 'Chip Builder' cloud tool that allows designers to configure these bespoke chips without traditional ASIC complexity. The discussion covers the technical architecture, cost structure via shuttle programs, and the strategic advantage of heterogeneous integration as Moore's Law slows.

The summary, chapters and topics are generated from the episode’s audio by this directory, not written by The Circuit. The episode itself belongs to its publisher.