EE Times Current

EE Times on the electronics industry, from semiconductors and AI hardware to design tools, for design engineers and other technology professionals.

278 episodes · 157 hours · since 2018

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EE Times Current is filed under electronics, engineering and hardware. Its most recent episode published on 7 Oct 2026, so it is still actively publishing. Listeners have left 28 ratings on Apple Podcasts, averaging 4.8 out of 5.

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Where to begin with EE Times Current: full episodes about building physical products, award winners first.

5 Jun 2026 · 41m
When AI Gets a Body: Physical AI, Humanoids and the Future of Silicon
Hezi Saar, Executive Director of Product Marketing at Synopsys, discusses the rise of Physical AI, focusing on the semiconductor demands of humanoid robots and autonomous systems. He explains the shift from cloud-only AI to hybrid inference architectures that balance latency, privacy, and cost, highlighting the 'memory wall' bottleneck in edge devices. Saar also details how open standards like MIPI CSE 2.0 and multi-die packaging are critical for reducing risk and enabling secure, scalable physical AI hardware.
Chips, FPGAs & semiconductors Embedded firmware
8 chapters
7 Mar 2025 · 48m
Making Analog Chip Designs Without Analog Designers
Dr. Jennifer Hasler of Georgia Tech discusses her work on Field Programmable Analog Arrays (FPAAs) and new Python-based analog synthesis tools designed to make analog chip design accessible to non-analog experts. She explains how floating-gate technology enables programmable analog circuits and argues for the importance of analog design in low-power edge AI applications. The episode also features commentary from Dr. Giulia D’Angelo and Professor Ralph Etienne-Cummings on the challenges of analog adoption and the recent Nobel Prize in Physics.
Analog & power electronics EDA & CAD tools
9 chapters
7 Aug 2026 · 23m
Beyond Automation: Self-Verifying AI Agents for Semiconductor and PCB Design
Amit Gupta, Chief AI Strategy Officer at Siemens EDA, and Tim Costa, VP and GM of Industrial and Computational Engineering at NVIDIA, discuss their collaboration to build self-verifying AI agents for semiconductor and PCB design. They explain how the Fuse EDA AI agent uses NVIDIA's GPU-accelerated libraries and Nemotron models to execute long-running engineering workflows while verifying outputs against physics-based EDA engines. The speakers highlight a specific case study with NVIDIA's silicon team, where the Salido characterization suite achieved a 10x reduction in turnaround time and token costs by automating manual setup and error handling. They outline three milestones for the future: workflow coverage, verified repeatability, and integration into core engineering infrastructure, aiming to cut tape-out schedules in half.
AI & machine learning Chips, FPGAs & semiconductors
9 chapters

Hear it in a few minutes

Single discussions from recent episodes, playing the show's own audio from where each begins.

Synopsys Foundation IP: reducing re-spin costs and improving PPA
5 min · EE Times Current
From “Beyond PPA: How Foundation IP Enables Predictable Execution and Lower TCO for AI-Era SoCs” at 3:49
The Future of Neuromorphic AI
6 min · EE Times Current
From “Why Computing With Time Gives Neuromorphic AI an Edge” at 35:24
Architectural Exploration and Virtual Platforms
4 min · EE Times Current
From “Where Software Meets Silicon: A Digital Twin Playbook” at 5:49

Latest episodes

7 Oct 2026 · 24m
Beyond PPA: How Foundation IP Enables Predictable Execution and Lower TCO for AI-Era SoCs
Ravi Todi, Executive Director of Product Management at Synopsys, explains that competitive power, performance, and area (PPA) are no longer sufficient for AI-era SoCs, as design complexity and execution risk at advanced nodes require a focus on predictable execution and total cost of ownership (TCO). He details how Synopsys' Foundation IP platform—integrating embedded memory, logic libraries, and I/O—reduces integration risks and avoids expensive re-spins, which can cost $20–$40 million in mask sets and delay tape-outs by 6–9 months. Todi highlights that this holistic approach enables first-pass silicon success, cross-foundry portability, and optimized PPA for both high-performance compute (HPC) and edge AI (HAI) designs, shifting the buying decision from lowest IP license price to lowest total cost of silicon on time.
Chips, FPGAs & semiconductors Pricing, margins & unit economics
7 chapters
18 Sept 2026 · 57m
Why Computing With Time Gives Neuromorphic AI an Edge
Dr. Ryad Benosman, co-founder of Prophesee and researcher at Johns Hopkins, explains why neuromorphic engineering and event-based vision offer a superior path for AI compared to traditional frame-based computer vision. He details his journey from pure mathematics to building event sensors, commercializing them through Prophesee, and developing retinal prosthetics using optogenetics and silicon implants. Benosman argues that computing with time allows for efficient, low-power processing that mimics biological systems, whereas current AI hits a wall due to power and data inefficiency.
AI & machine learning Sensors & measurement in products
8 chapters
4 Sept 2026 · 23m
Where Software Meets Silicon: A Digital Twin Playbook
VJ Chobisa, Senior Director at Siemens EDA, explains how digital twins and virtual platforms enable early software-hardware co-development to address system-level verification challenges in massive designs. He details the transition from architectural exploration to emulation and FPGA prototyping, highlighting how connected platforms help teams find power, performance, and DFT issues before tapeout. Chobisa argues that digital twins extend beyond electronics to model entire systems, such as automotive scenarios involving sensors and actuators, ensuring safety and reliability in complex products.
Connected products & IoT Debugging & failure analysis
6 chapters
26 Aug 2026 · 24m
Trust at Scale: The Next Challenge for AI-Driven Semiconductor Development
Dr. Jim Shiely, Chief of Staff for Calibre Semiconductor R&D at Siemens EDA, discusses the 'trust bottleneck' emerging in semiconductor development as AI becomes embedded in engineering workflows. He explains that while AI accelerates tasks, it creates an overflow of data that requires 'trustworthy engineering intelligence'—grounded in independent verification tools like Calibre and physics-based models—to prevent hallucinations and ensure decision confidence. Shiely argues that successful companies will use digital twins and agentic flows to provide structured, traceable intelligence rather than just raw data, enabling humans to make rapid, confident decisions in a high-pressure environment.
AI & machine learning Chips, FPGAs & semiconductors
7 chapters
25 Aug 2026 · 1h 00m
Do Spikes Need Common Language for Sensing and Learning?
Dr. Sunny Bains chairs a panel at the University of Sussex featuring Dr. Chiara Bartolozzi (Italian Institute of Technology), Dr. Federico Corradi (Eindhoven University of Technology), Dr. James Knight (University of Sussex), Dr. Laura Kriener (Institute of Neuroinformatics, Zurich), and Dr. Sebastian Siegel (Peter Grünberg Institute, Jülich) to debate whether spikes provide a common language for sensing and learning. The panelists argue that while spikes offer energy efficiency, the field lacks a unified encoding scheme to integrate multimodal data, such as combining event-based vision with frame-based imaging or touch sensors. They discuss the commercial trajectory of neuromorphic engineering, highlighting early adoption in edge IoT and drones by companies like Okterov and Kinema, while emphasizing the need for co-design of hardware and algorithms to solve complex robotic tasks.
Embedded firmware Sensors & measurement in products
11 chapters
21 Aug 2026 · 18m
Designing the AI Factory from the Rack Up
Neeraj Paliwal, Senior Vice President of Silicon IP Product Management at Synopsys, explains why the AI rack has replaced the data center as the fundamental unit of design and economics. He details the shift from 8kW to 130kW+ power densities in systems like NVIDIA's GB200 NVL72, driven by the need to optimize cost per token across distributed GPUs. Paliwal highlights that the industry is moving past single-die limits toward 3D stacking, custom HBM memory integration, and high-speed die-to-die interfaces like UCIe to overcome the memory and I/O bandwidth walls.
Chips, FPGAs & semiconductors Batteries & low-power design
5 chapters
22 Jul 2026 · 58m
Can Great Sky’s Light-Connected AI Enable Bigger Brains?
Dr. Jeff Shainline, founder of Great Sky, explains how his company combines superconducting electronics with photonic interconnects to build neuromorphic AI hardware that operates at 4 Kelvin. He details the use of Josephson junctions, SQUIDs, and single-photon detectors to achieve extreme speed and energy efficiency, arguing that this architecture offers a 300x cost advantage for large language models compared to NVIDIA's GB 200 systems. The discussion covers manufacturing partnerships with companies like Seek and IMEC, the roadmap to wafer-scale integration, and the physical limits of cognition defined by light-speed communication.
Mechanical engineering AI & machine learning
9 chapters
27 Jun 2026 · 32m
Under the Hood of Intelligent Systems
Hezzy Sar, Executive Director of Product Management at Synopsys and Chair of the MIPI Alliance Board, discusses how the MIPI Alliance is evolving interface standards from mobile phones to automotive, industrial, and physical AI applications. He details specific protocols like MIPI AFI for automotive connectivity, CSI-2 features such as Smart Region of Interest (SROI) and Event Sensing and Processing (ESP), and DSI advancements for XR displays. The conversation highlights the importance of low-power, high-efficiency connectivity and the new security frameworks being integrated into these standards to ensure end-to-end protection for autonomous systems.
Wireless & RF Sensors & measurement in products
7 chapters
8 Jun 2026 · 46m
Will Photonics Loosen the Bottlenecks in Neural Systems?
Dr. Patty Stabile of Eindhoven University of Technology explains her all-optical neuromorphic computing architecture using semiconductor optical amplifiers and wavelength division multiplexing to achieve ultra-low latency processing without optical-to-electrical conversion. Hosts Dr. Sonny Baines and Dr. Juliette D’Angelo discuss the scalability, power efficiency, and material challenges of indium phosphide versus silicon photonics, while Professor Ralph Etienne-Cummings of Johns Hopkins University critiques the current state of the field and highlights applications in autonomous vehicles and 6G signal processing.
AI & machine learning Chips, FPGAs & semiconductors
8 chapters

Every episode

276 episodes with a summary and chapters, by year.

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202053 episodes

201961 episodes

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