Hardware Podcasts

Leading Edge Analog with Joren Vaes

The Amp Hour · 18 Oct 2025 · 1h 04m · Episode 706

What this episode covers

Joren Vaes, a high-speed design engineer at SOFICS, explains the complexities of designing analog IP blocks for leading-edge semiconductor nodes like TSMC's 2 nm process. He details how designers navigate massive Process Design Kits (PDKs) with thousands of rules, utilizing advanced simulation tools from Cadence, Synopsys, and Siemens to manage parasitics across 18+ metal layers. The conversation covers the transition from FinFET to nanosheet architectures and the use of on-chip passive components, such as transformers, to achieve impedance matching at frequencies up to 50 GHz. Vaes also describes the rigorous verification workflow, including Design Rule Checks (DRC), Layout Versus Schematic (LVS), and parasitic extraction, which are critical before tape-out to millions of dollars in mask costs.

Most relevant to

early-stage companies

Topics

Mentioned

Companies
SOFICS, TSMC, Siemens, Global Foundries, Intel, Samsung Foundry
Tools
Cadence, Synopsys

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