Hardware Podcasts

Automated Multiphysics for 3D IC Success

EE Times Current · 6 Mar 2026 · 28m

What this episode covers

Chevanoki and John Ferguson from Siemens EDA discuss the challenges of automated multiphysics analysis for 3D IC design, specifically how power, heat, and stress interact in stacked heterogeneous architectures. They explain the shift from traditional 2D verification to integrated flows that account for GDS-level details, thermal impacts, and mechanical stresses to ensure timing closure and reliability. The guests highlight the importance of standards like 3D-BC, the use of Siemens' Calibre and Flowtherm tools, and the future role of AI in reducing the steep learning curve for designers moving into 3D stacking.

Most relevant to

large enterprises

Topics

Mentioned

Companies
Siemens EDA, TSMC, IEEE
Products
Calibre, Flowtherm
Also
3D-BC

Related episodes from other shows

Other shows on the same ground, closest first.

  • Moore's Lobby · 55m

    Inside a Multi-$Billion IP Engine Driving IC and EDA Innovations

    John Koeter, Senior Vice President of IP at Synopsys, discusses the evolution of semiconductor intellectual property, the shift to multi-die chiplet architectures, and the transformative role of AI in chip design. He details Synopsys' acquisition of Ansys to enhance thermal modeling for 3D ICs, the challenges of managing heat in stacked dies, and the critical importance of software ecosystems for emerging architectures like RISC-V. Koeter also offers career advice on adaptability and leveraging AI as a force multiplier for engineers.

    Chips, FPGAs & semiconductorsAI & machine learning
    9 chapters

  • The Circuit · 33m

    Episode 38: The Future of Transistor Design and Advanced Packaging

    Huiming Bu from IBM Research discusses the future of transistor design and advanced packaging with host Ben Bajarin. They explore the industry's transition from FinFET to nanosheet architectures and the emergence of 3D scaling via Vertical Transport FETs (VTFET) and Stacked FETs (SFET). Bu explains how chiplet technology and heterogeneous integration are accelerating compute density, allowing AMD's MI300X to reach 100 billion transistors seven years ahead of traditional scaling predictions. The conversation highlights the critical need for System Technology Co-optimization (STCO) and new EDA tools to manage the complexity of 2.5D and 3D IC designs.

    Chips, FPGAs & semiconductorsManufacturing partners & offshoring
    6 chapters

  • The Circuit · 42m

    Episode 67: A Conversation with Aart de Geus on EDA and the Future of Silicon Design

    Aart de Geus, co-founder and executive chair of Synopsys, discusses the evolution of electronic design automation (EDA) and the future of silicon design. He explains how the industry shifted from analog to digital design, enabling the automation that drove Moore's Law, and details the transition to the Angstrom era with technologies like FinFETs and backside power delivery. De Geus also highlights the rise of systemic complexity through chiplets and vertical stacking, and the critical role of AI in optimizing these complex multi-die architectures.

    EDA & CAD toolsAI & machine learning
    8 chapters

  • The Amp Hour · 1h 07m

    Downward Sloping Trace

    Dave Jones and Chris Gammell discuss the 'design deja vu' of independently creating nearly identical 1996 logic analyzer projects using Lattice Semiconductor CPLDs, and the technical nuances of timing vs. state analysis. They then detail the thermal design challenges of Jones's 'Micro Supply' project, explaining the decision to use a custom die-cast heat sink and plastic enclosure to achieve high volumetric efficiency. The conversation concludes with a critique of KiCad's via placement workflow and a recommendation for the book 'The Practicing Mind'.

    Mechanical engineeringDebugging & failure analysis
    6 chapters

  • Moore's Lobby · 1h 01m

    Synopsys' Stelios Diamantidis Is Bringing the Magic of AI To Chip Design

    Stelios Diamantidis, Distinguished Architect at Synopsys, discusses the evolution of chip design from manual processes to AI-driven optimization. He recounts his career journey, including founding two EDA startups focused on verification and Silicon Lifecycle Management (SLM), before joining Synopsys to lead the development of DSO.ai. Diamantidis explains how reinforcement learning is used to solve intractable physical design problems, optimizing power, performance, and area (PPA) for diverse verticals like CPUs, GPUs, and automotive chips.

    AI & machine learningEDA & CAD tools
    8 chapters

The summary, chapters and topics are generated from the episode’s audio by this directory, not written by EE Times Current. The episode itself belongs to its publisher.