Synopsys' Stelios Diamantidis Is Bringing the Magic of AI To Chip Design

DesignDSO.ai (Design Space Optimization using AI)reduced leakage 15-25% and cell area 15% in some cases

Synopsys used reinforcement learning to automatically optimize physical chip design parameters, allowing the AI to explore design spaces and optimize outcomes like power, performance, and area beyond what engineers could manually achieve.

“I'm extremely excited that this capability, this technology has provided a framework for all of them. No exceptions so far. To actually come up with great solutions, right? No matter what the problem.”

Engineering & simulationDSO.airun 10s of experiments at any given time

The AI tool was integrated into the physical design flow to run synthesis and place-and-route, optimizing the workflow by treating it as a reinforcement learning environment to identify solutions engineers lacked time to find.

“So now for the past 2.5 years, There's been this product out there that can plug into any physical design flow that runs synthesis and place route and help designers optimize that workflow by treating it as a reinforcement learning environment.”

Engineering & simulationreinforcement learning

Engineers used reinforcement learning to teach a software agent to optimize clock tree construction by adjusting parameters and measuring quality, serving as the first proof of concept for AI in chip design.

“So the very 1st proof of concept that reinforcement learning care work and chip design came out of, essentially, giving a piece of software the ability to play with clock creation parameters, measure clock quality based on whatever parameters you try to tweak.”