Hardware Podcasts

Accessible ASICs with Andreas Olofsson

The Amp Hour · 13 Nov 2023 · 1h 03m · Episode 650

What this episode covers

Andreas Olofsson, CEO of ZeroASIC, discusses his journey from founding Parallela and working at DARPA to launching ZeroASIC, a company that builds custom ASICs using chiplets. He explains how the high cost of traditional tape-outs and IP licensing creates barriers for mid-sized companies, and how ZeroASIC’s platform allows users to drag-and-drop pre-designed chiplets (including RISC-V CPUs, FPGAs, and ML accelerators) to create a functional device in weeks rather than months. The episode highlights ZeroASIC’s e-fabric interposer technology and their cloud-based emulation service that lets customers test their custom silicon designs on AWS FPGAs before manufacturing.

Most relevant to

early-stage companies

Topics

Mentioned

Companies
ZeroASIC, DARPA, AWS, ARM, NVIDIA, TSMC, ASML, Raspberry Pi, Intel, UC San Diego
Products
Parallela
Chips
RISC-V
Tools
Silicon Compiler, OpenROAD

Related episodes from other shows

Other shows on the same ground, closest first.

  • Embedded.fm · 1h 15m

    454: Printf Hello

    Uri Shaked, creator of Wokwi and Tiny Tapeout, explains how Tiny Tapeout democratizes ASIC design by leveraging open-source PDKs and a shared mask strategy to offer chip manufacturing for around $100. He details the technical challenges of building Wokwi, a web-based simulator for embedded systems, including reverse-engineering processor instruction sets and complex peripheral behaviors like SHA and SPI. Shaked also outlines his business strategy, which involves selling space on silicon via Tiny Tapeout and offering Wokwi through a freemium model, VS Code integration, and an on-premise CI/CD solution for professional users.

    Embedded firmwareChips, FPGAs & semiconductors
    8 chapters

  • Embedded.fm · 57m

    322: Learn Assembly Code

    Ramiro Montes de Oca, CEO and founder of aThing.io, explains his company's 'motionless electronics'—modular, penny-sized components that connect via phone-style connectors without soldering. He discusses the technical architecture of these modules, the emerging chiplet industry standard led by the Chiplet Alliance, and the business challenges of scaling hardware manufacturing during global supply chain disruptions. Montes de Oca also shares insights from exhibiting at CES and the importance of design-for-manufacturing for early-stage founders.

    PCB design & layoutChips, FPGAs & semiconductors
    8 chapters

  • The Circuit · 40m

    EP 123: Marvell ASIC TAM, ASIC Challenges Remain, More Semi 2.0

    Ben Bajarin and Jay Goldberg discuss Marvell's recent custom semiconductor event, analyzing their technical differentiation against Broadcom and the challenges of the lumpy, cyclical nature of custom ASIC revenue. They explore the strategic tension between GPUs and ASICs, noting that hyperscalers like Amazon and Google are playing both sides, while examining the rising costs of leading-edge foundry services and the economic shift toward chiplet architectures. The conversation concludes with a thesis on 'Semi 2.0,' driven by AI workloads outstripping compute capacity, and the physical limits of monolithic chip scaling due to skyrocketing wafer prices.

    Chips, FPGAs & semiconductorsPricing, margins & unit economics
    8 chapters

  • EE Times Current · 19m

    Risking RISC-V | Engineers & the Gig Economy | Chiplets

    Brian Santo discusses RISC-V's potential in smartphones, highlighting Qualcomm's investment in SiFive and its shift from IP licensing to silicon production. The episode explores engineering education at Olin College, emphasizing a broader curriculum integrating ethics and liberal arts, and examines the emerging chiplet ecosystem, noting technical hurdles like testing and thermal management identified by Intel's Ramuni Nagasetti. Finally, it recounts the history of Texas Instruments' Speak & Spell and the current activities of inventor Jean Franzon.

    Chips, FPGAs & semiconductorsCareers & education
    5 chapters

  • The Spark Gap · 57m

    The Spark Gap - Episode 29

    Dr. Fouad Kiamilev from the University of Delaware explains the design of application-specific integrated circuits (ASICs), detailing a high-power display projector chip with 250,000 I/Os and liquid nitrogen cooling. He describes the iterative development process, from a 64x64 test chip to a 512x512 production module costing $250,000, and the use of Cadence tools for full-custom layout. Kiamilev also discusses the importance of physical health, fitness, and work-life balance in sustaining long-term engineering productivity and avoiding burnout.

    Chips, FPGAs & semiconductorsCareers & education
    8 chapters

The summary, chapters and topics are generated from the episode’s audio by this directory, not written by The Amp Hour. The episode itself belongs to its publisher.