Hardware Podcasts

Can Neuromorphic Be Low-Power, Reconfigurable, and Scalable?

EE Times Current · 14 Jul 2025 · 50m

What this episode covers

Professor Gert Cauwenberghs of the University of California San Diego, leading the Neuromorphic Commons (Thor) hub, explains his approach to building brain-scale neuromorphic systems that are low-power, reconfigurable, and scalable. He details the design of the integrate-and-fire transceiver array (IFAT) and the Neuram chip, which uses resistive random access memory (RRAM) crossbars to achieve femtojoule-per-synapse efficiency, and the Hierarchical Address Event Representation (HiAER) system, which scales to 160 million neurons on FPGA infrastructure. The discussion also covers his work on 'irritables'—wearable ear devices for non-invasive brain monitoring and neurofeedback—and a debate with Professor Ralph Etienne-Cummings on whether neuromorphic neurons should be analog or digital.

Most relevant to

early-stage companies

Topics

Mentioned

Companies
Cogionic Systems
Products
IFAT, Neuram, HiAER, Spinnaker 2, LuLu, CGX
Chips
FPGA, HBM, RRAM
Also
Neuromorphic Commons, Thor

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